-----Original Message-----
From: Greg A. Woods <woods@most.weird.com>
Newsgroups: hanse-ml.netbsd.port-i386
To: port-i386@netbsd.org <port-i386@netbsd.org>
Date: Tuesday, June 30, 1998 12:14 AM
Subject: Re: About SMP


>[ On , June 24, 1998 at 11:54:05 (GMT), Heiko W.Rupp wrote: ]
>> Subject: Re: About SMP
>>
>> In a recent german c't magazine, they explained it with the fact, that
you
>> need some specific interrupt register/controller on the cpu. Intel uses
>> its proprietary controller for this, while the others adhere to some
>> open standard. Dunno if this is right though.
>
>In reading through the data sheets for the Intel 440LX chipset today I
>discovered what appear to be some rudiments of support for redundant CPU
>support -- i.e. a master/slave dual-CPU scenario where one CPU checks
>the results of the other and reports any discrepancies through the SMB.
>
>That's as far as I got though -- just a hint of a possibility....
>
>--
> Greg A. Woods
>
>+1 416 443-1734      VE3TCP      <gwoods@acm.org>      <robohack!woods>
>Planix, Inc. <woods@planix.com>; Secrets of the Weird <woods@weird.com>