> ENTRY(idle)
>         cli
>         movl    _C_LABEL(whichqs),%ecx
>         testl   %ecx,%ecx
>         jnz     sw1
>         sti
> #if NAPM > 0
>         call    _C_LABEL(apm_cpu_idle)
> #endif
>         hlt
> #if NAPM > 0
>         call    _C_LABEL(apm_cpu_busy)
> #endif
>         jmp     _C_LABEL(idle)

It seems to me there's a race here.  If an interrupt occurs after the
sti and before the hlt, the machine can block when it shouldn't.

Presumably the flag setting from the sti is delayed by at least one
instruction, or the race would be unavoidable (and on other
architectures I've seen such things done for just that reason).  But if
NAPM>0, there's a potentially long time between the sti and the hlt.
What am I missing?

					der Mouse

			       mouse@rodents.montreal.qc.ca
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