On Thu, Sep 12, 2002 at 08:56:08AM +1200, Gregory McGarry wrote:
> David Laight wrote:
> 
> > Has anyone seen/read any references to the interrupt latency
> > inherent in any of the recent Intel cpus?
> > 
> > Note, I'm not interested in the OS latency, I want to know how
> > much of the interrupted code gets executed before the first instruction
> > of the interrupt handler.  In particular if an interrupt is pending
> > but the I flag is clear and you then set it, what value of the PC
> > will be stacked.
> >
> > With the code below my athlon takes the pending interrupt after
> > the 'nop' (as expected).
> > 
> > 	cli
> > 	nop			# cli page says interrupt happens here...
> > 	test	$1,memory	# look at data ISR would set.
> > 	jnz	...
> > 
> > However a P2 takes it way, way later...
> 
> cli disables interrupts.  sti enables interrupts.

Just a typo...

> 
> I would guess the restarted instruction would depend on the
> CPU's instruction stream reordering.  Expecting an interrupt to
> occur at a specific instruction sounds like something that should
> be avoided.

Sometimes you need to do things that should be avoided :-)

I've just had an idea!  Wonder what happens with:
	sti
	nop
	cli
	sti


	David

-- 
David Laight: david@l8s.co.uk