Subject: Re: CeleronM cache info
To: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
From: Tetsuya Isaki <isaki@par.odn.ne.jp>
List: port-i386
Date: 07/05/2007 22:56:53
Tsutsui-san,
Thank you for reviewing. commited.
At Fri, 29 Jun 2007 23:14:34 +0900,
Izumi Tsutsui wrote:
> > The patch prints cache information of CeleronM (600MHz,
> > no processor number). Do you review it, please?
> > If there is no objection, I'll commit it next weekend.
> >
> > --- sys/arch/i386/i386/identcpu.c 19 Jun 2007 14:16:56 -0000 1.67
> > +++ sys/arch/i386/i386/identcpu.c 24 Jun 2007 01:41:14 -0000
> > @@ -62,8 +62,10 @@
> > static const struct x86_cache_info
> > intel_cpuid_cache_info[] = {
> > { CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL },
> > + { CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL },
> > { CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL },
> > { CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL },
> > + { CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL },
> > { CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL },
> > { CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" },
> > { CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" },
> > @@ -99,6 +101,7 @@
> > { CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL },
> > { CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL },
> > { CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL },
> > + { CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL },
> > { 0, 0, 0, 0, 0, NULL },
> > };
>
> I think it's okay to commit since it's comfirmed on your machine
> and these values are also used on FreeBSD:
> http://www.jp.freebsd.org/cgi/cvsweb.cgi/src/sys/i386/i386/identcpu.c
>
> I wonder if it's better to take more other values from FreeBSD
> and sort them by cai_desc (or cia_index) though.
---
Tetsuya Isaki <isaki@par.odn.ne.jp / isaki@NetBSD.org>