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Hi,

Here is a small patch to update AMD cpu specific features for RDTSCP
instruction; found, at least, on `Dual-Core AMD Opteron Processor 8218'.

Support for this instruction can be checked on register edx bit 27
for CPUID 0x80000001.

cpu0: Dual-Core AMD Opteron(tm) Processor 8218, 2612.17 MHz
cpu0: features: ffdbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features: ffdbfbff<PGE,MCA,CMOV,PAT,PSE36,MPC,NOX,MMXX,MMX>
cpu0: features: ffdbfbff<FXSR,SSE,SSE2,RDTSCP,HTT,LONG,3DNOW2,3DNOW>
cpu0: features2: 2001<SSE3>
cpu0: I-cache 64 KB 64B/line 2-way, D-cache 64 KB 64B/line 2-way
cpu0: L2 cache 1 MB 64B/line 16-way
cpu0: ITLB 32 4 KB entries fully associative, 8 4 MB entries fully associative
cpu0: DTLB 32 4 KB entries fully associative, 8 4 MB entries fully associative

-- 
Nicolas Joly

Biological Software and Databanks.
Institut Pasteur, Paris.

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Index: sys/arch/x86/include/specialreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/specialreg.h,v
retrieving revision 1.17
diff -u -r1.17 specialreg.h
--- sys/arch/x86/include/specialreg.h	3 Jul 2007 17:07:55 -0000	1.17
+++ sys/arch/x86/include/specialreg.h	6 Jul 2007 14:05:31 -0000
@@ -146,13 +146,14 @@
 #define CPUID_MPC	0x00080000	/* Multiprocessing Capable */
 #define CPUID_NOX	0x00100000	/* No Execute Page Protection */
 #define CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
+#define CPUID_RDTSCP	0x08000000	/* Read TSC Pair Instruction */
 #define CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
 #define CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
 
 #define CPUID_EXT_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
 				    "\24MPC\25NOX\26B21\27MMXX\30MMX"
-#define CPUID_EXT_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \
-				    "\0373DNOW2\0403DNOW"
+#define CPUID_EXT_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \
+				    "\36LONG\0373DNOW2\0403DNOW"
 
 /*
  * Centaur Extended Feature flags

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