Intel G43 integrated graphics on -current

[Brad du Plessis <bradd%cat.co.za@localhost>]

Hi all,

Please advise if this should be posted elsewhere.

I've been fiddling with netbsd-current source in an attempt to get the 
integrated graphics device working. I've managed to get it working with 
the intel driver in xorg (xf86-video-intel version 2.4.2), see the 
kernel patch below (please excuse my pcidevs naming and other unrelated 
pcidevs are included for other stuff I've been trying to get working the 
the motherboard, DG43NB). One of the things I'm a little bit unsure of 
is the mapping of the mmadr registers. From the G43 datasheets I 
downloaded it appears to be slightly different when compared to the 
G33/Q35 implementation. See this excerpt from 'Intel(R) 4 Series Chipset 
Family' the datasheet:

*snip*
GTTMMADR—Graphics Translation Table, Memory Mapped
Range Address
B/D/F/Type: 0/2/0/PCI
Address Offset: 10-17h
Default Value: 0000000000000004h
Access: R/W, RO
Size: 64 bits

This register requests allocation for combined Graphics Translation 
Table Modification
Range and Memory Mapped Range. The space is 4 MB combined for MMIO and 
Global
GTT table aperture (512 KB for MMIO and 2 MB for GTT). GTTADR will be at
(GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR.
*snip*

So from what I can gather, the MMIO base address is still 0x10 and the 
GTTADR offset 2MB into the memory map. Please check the code below, not 
sure if this is correct, but it seems to be working. I don't really know 
what I'm doing but I really want to get this working :) .


Thanks,
Brad


Here's the relevant section of dmesg:

*snip*
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0
pchb0: vendor 0x8086 product 0x2e20 (rev. 0x03)
agp0 at pchb0: detected 30716k stolen memory
agp0: aperture at 0xc0000000, size 0x10000000
vga1 at pci0 dev 2 function 0: vendor 0x8086 product 0x2e22 (rev. 0x03)
vga1: WARNING: ignoring 64-bit BAR @ 0x10
vga1: WARNING: ignoring 64-bit BAR @ 0x18
*snip*

Here's the patch:

Index: agp.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/agp.c,v
retrieving revision 1.61
diff -u -r1.61 agp.c
--- agp.c 22 Aug 2008 18:05:44 -0000 1.61
+++ agp.c 1 Oct 2008 10:08:52 -0000
@@ -177,11 +177,13 @@
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q35_HB,
NULL, agp_i810_attach },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G33_HB,
- NULL, agp_i810_attach },
+ NULL, agp_i810_attach },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q33_HB,
NULL, agp_i810_attach },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82946GZ_HB,
NULL, agp_i810_attach },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G43_HB,
+ NULL, agp_i810_attach },
#endif

#if NAGP_INTEL > 0
Index: agp_i810.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/agp_i810.c,v
retrieving revision 1.56
diff -u -r1.56 agp_i810.c
--- agp_i810.c 22 Aug 2008 18:05:44 -0000 1.56
+++ agp_i810.c 1 Oct 2008 10:08:52 -0000
@@ -59,7 +59,7 @@
#define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
#define WRITEGTT(off, v) \
do { \
- if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \
+ if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33 || 
isc->chiptype == CHIP_G43) { \
bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \
(u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \
(v)); \
@@ -80,6 +80,7 @@
#define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
#define CHIP_I965 4 /* 965Q/965PM */
#define CHIP_G33 5 /* G33/Q33/Q35 */
+#define CHIP_G43 6 /* BRAD - G43 */

struct agp_i810_softc {
u_int32_t initial_aperture; /* aperture size at startup */
@@ -161,6 +162,8 @@
case PCI_PRODUCT_INTEL_82965PM_IGD_1:
case PCI_PRODUCT_INTEL_82G33_IGD:
case PCI_PRODUCT_INTEL_82G33_IGD_1:
+ case PCI_PRODUCT_INTEL_82G43_IGD:
+ case PCI_PRODUCT_INTEL_82G43_IGD_1:
case PCI_PRODUCT_INTEL_82965G_IGD:
case PCI_PRODUCT_INTEL_82965G_IGD_1:
case PCI_PRODUCT_INTEL_82Q35_IGD:
@@ -269,11 +272,16 @@
case PCI_PRODUCT_INTEL_82Q33_IGD_1:
isc->chiptype = CHIP_G33;
break;
+ case PCI_PRODUCT_INTEL_82G43_IGD:
+ case PCI_PRODUCT_INTEL_82G43_IGD_1:
+ isc->chiptype = CHIP_G43;
+ break;
}

switch (isc->chiptype) {
case CHIP_I915:
case CHIP_G33:
+ case CHIP_G43:
apbase = AGP_I915_GMADR;
break;
default:
@@ -291,7 +299,22 @@
return error;
}

- if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) {
+ if (isc->chiptype == CHIP_G43)
+ {
+ error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR,
+ PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
+ &mmadr, &mmadrsize);
+ if (error != 0) {
+ aprint_error(": can't map mmadr registers\n");
+ agp_generic_detach(sc);
+ return error;
+ }
+
+ isc->gtt_bsh=isc->bsh;
+ isc->gtt_bst=isc->bst + (2*1024*1024);
+ }
+ else if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33)
+ {
error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR,
PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
&mmadr, &mmadrsize);
@@ -438,7 +461,8 @@

gatt->ag_physical = pgtblctl & ~1;
} else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
- isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) {
+ isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
+ isc->chiptype == CHIP_G43) {
pcireg_t reg;
u_int32_t pgtblctl, stolen;
u_int16_t gcc1;
@@ -474,6 +498,9 @@
return EINVAL;
}
break;
+ case CHIP_G43:
+ stolen = 2048 + 4;
+ break;
default:
aprint_error(": bad chiptype\n");
agp_generic_detach(sc);
@@ -597,6 +624,7 @@
return 128 * 1024 * 1024;
case CHIP_I915:
case CHIP_G33:
+ case CHIP_G43:
reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC);
msac = (u_int16_t)(reg >> 16);
if (msac & AGP_I915_MSAC_APER_128M)
Index: pcidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.959
diff -u -r1.959 pcidevs.h
--- pcidevs.h 28 Sep 2008 11:36:06 -0000 1.959
+++ pcidevs.h 1 Oct 2008 10:08:54 -0000
@@ -2214,6 +2214,7 @@
#define PCI_PRODUCT_INTEL_82801I_IFE_GT 0x10c3 /* 82801I (GT) LAN 
Controller */
#define PCI_PRODUCT_INTEL_82801H_IFE_GT 0x10c4 /* i82801H IFE (GT) LAN 
Controller */
#define PCI_PRODUCT_INTEL_82801H_IFE_G 0x10c5 /* i82801H IFE (G) LAN 
Controller */
+#define PCI_PRODUCT_INTEL_82567V 0x10ce /* i82567V LAN controller */
#define PCI_PRODUCT_INTEL_82815_DC100_HUB 0x1100 /* 82815 Hub */
#define PCI_PRODUCT_INTEL_82815_DC100_AGP 0x1101 /* 82815 AGP */
#define PCI_PRODUCT_INTEL_82815_DC100_GRAPH 0x1102 /* 82815 Graphics */
@@ -2493,6 +2494,9 @@
#define PCI_PRODUCT_INTEL_82801H_HDA 0x284b /* 82801H High Definition 
Audio Controller */
#define PCI_PRODUCT_INTEL_82801H_THERMAL 0x284f /* 82801H Thermal 
Controller */
#define PCI_PRODUCT_INTEL_82801IH_LPC 0x2912 /* 82801IH LPC Interface 
Bridge */
+#define PCI_PRODUCT_INTEL_82801I_ICH10 0x3a18 /* BRAD */
+#define PCI_PRODUCT_INTEL_82801I_ICH10_SATA_1 0x3a20
+#define PCI_PRODUCT_INTEL_82801I_ICH10_SATA_2 0x3a26
#define PCI_PRODUCT_INTEL_82801IO_LPC 0x2914 /* 82801IO LPC Interface 
Bridge */
#define PCI_PRODUCT_INTEL_82801IR_LPC 0x2916 /* 82801IR LPC Interface 
Bridge */
#define PCI_PRODUCT_INTEL_82801IB_LPC 0x2918 /* 82801IB LPC Interface 
Bridge */
@@ -2502,6 +2506,7 @@
#define PCI_PRODUCT_INTEL_82801I_SATA_AHCI4 0x2923 /* 82801I AHCI SATA 
Controller with 4 ports */
#define PCI_PRODUCT_INTEL_82801I_SATA_3 0x2926 /* 82801I SATA Controller 
with 2 ports */
#define PCI_PRODUCT_INTEL_82801I_SMB 0x2930 /* 82801I SMBus Controller */
+#define PCI_PRODUCT_INTEL_82801I_SMB_ICH10 0x3a30 /* BRAD 82801I SMBus 
Controller */
#define PCI_PRODUCT_INTEL_82801I_THERMAL 0x2932 /* 82801I Thermal 
Controller */
#define PCI_PRODUCT_INTEL_82801I_USB_1 0x2934 /* 82801I USB UHCI 
Controller */
#define PCI_PRODUCT_INTEL_82801I_USB_2 0x2935 /* 82801I USB UHCI 
Controller */
@@ -2537,7 +2542,10 @@
#define PCI_PRODUCT_INTEL_82G33_EXP 0x29c1 /* 82G33 PCI Express Port */
#define PCI_PRODUCT_INTEL_82G33_IGD 0x29c2 /* 82G33 Integrated Graphics 
Device */
#define PCI_PRODUCT_INTEL_82G33_IGD_1 0x29c3 /* 82G33 Integrated 
Graphics Device */
-#define PCI_PRODUCT_INTEL_82801I_LAN 0x29c4 /* 82801I LAN Controller */
+#define PCI_PRODUCT_INTEL_82G43_HB 0x2e20 /* BRAD 82G43/P45 Host Bridge */
+#define PCI_PRODUCT_INTEL_82G43_IGD 0x2e22 /* 82G43 Integrated Graphics 
Device */
+#define PCI_PRODUCT_INTEL_82G43_IGD_1 0x2e23 /* 82G43 Integrated 
Graphics Device */
+#define PCI_PRODUCT_INTEL_82801I_LAN 0x29c4 /* 82801I LAN Controller */
#define PCI_PRODUCT_INTEL_82Q33_HB 0x29d0 /* 82Q35 Host Bridge */
#define PCI_PRODUCT_INTEL_82Q33_EXP 0x29d1 /* 82Q35 PCI Express Bridge */
#define PCI_PRODUCT_INTEL_82Q33_IGD 0x29d2 /* 82Q35 Integrated Graphics 
Device */
Index: pchb.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/pci/pchb.c,v
retrieving revision 1.14
diff -u -r1.14 pchb.c
--- pchb.c 22 Aug 2008 18:05:44 -0000 1.14
+++ pchb.c 1 Oct 2008 10:49:31 -0000
@@ -382,6 +382,7 @@
case PCI_PRODUCT_INTEL_82Q35_HB:
case PCI_PRODUCT_INTEL_82G33_HB:
case PCI_PRODUCT_INTEL_82Q33_HB:
+ case PCI_PRODUCT_INTEL_82G43_HB:
/*
* The host bridge is either in GFX mode (internal
* graphics) or in AGP mode. In GFX mode, we pretend