Re: cpu0: L2 cache 0MB 64B/line 4-way for CeleronD

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

> cpuctl shows 0MB L2 cache size for CeleronD, specifially 
> two different models of 336 and 351 like as;
 :
> cpu0: L2 cache 0MB 64B/line 4-way

It should be 128KB or 256KB but seems truncated due to
too small printf buffer.


Index: usr.sbin/cpuctl/arch/i386.c
===================================================================
RCS file: /cvsroot/src/usr.sbin/cpuctl/arch/i386.c,v
retrieving revision 1.15
diff -u -r1.15 i386.c
--- usr.sbin/cpuctl/arch/i386.c 12 Mar 2009 09:10:15 -0000      1.15
+++ usr.sbin/cpuctl/arch/i386.c 16 Mar 2009 09:36:19 -0000
@@ -83,7 +83,7 @@
 #include "../cpuctl.h"
 
 /* Size of buffer for printing humanized numbers */
-#define HUMAN_BUFSIZE 5
+#define HUMAN_BUFSIZE sizeof("999KB")
 
 #define       x86_cpuid(a,b)  x86_cpuid2((a),0,(b))
 


---
Izumi Tsutsui