patch: make FSB frequency detection work on some Core processors

[denbrok%uni-bonn.de@localhost]

Hello,

attached patch makes bus speed detection work on my Core2Duo. There
may be further model numbers for which this method works. In case
there are further P3-based processors with the same model number
but differing extmodel numbers, this would also fix a wrong bus
speed to be detected for processor with extmodel != 0.

Regards,

Dennis den Brok

Index: sys/arch/x86/x86/intel_busclock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/intel_busclock.c,v
retrieving revision 1.5.10.3
diff -u -r1.5.10.3 intel_busclock.c
--- sys/arch/x86/x86/intel_busclock.c   18 Dec 2009 05:55:23 -0000      1.5.10.3
+++ sys/arch/x86/x86/intel_busclock.c   19 Apr 2010 15:38:53 -0000
@@ -92,7 +92,7 @@
        uint64_t msr;
        int bus, bus_clock = 0;
 
-       switch (CPUID2MODEL(ci->ci_signature)) {
+       switch (CPUID2MODEL(ci->ci_signature) + 
(CPUID2EXTMODEL(ci->ci_signature) << 4)) {
        case 0x9: /* Pentium M (130 nm, Banias) */
                bus_clock = 10000;
                break;
@@ -126,19 +126,8 @@
                }
                break;
        case 0xe: /* Core Duo/Solo */
-               /*
-                * XXX
-                * Newer CPUs will GP when attemping to access MSR_FSB_FREQ.
-                * In the long-term, use ACPI instead of all this.
-                */
-               switch (CPUID2EXTMODEL(ci->ci_signature)) {
-               case 0x1:
-                       aprint_debug("%s: unable to determine bus speed",
-                           device_xname(ci->ci_dev));
-                       goto print_msr;
-               }
-               /* FALLTHROUGH */
        case 0xf: /* Core Xeon */
+       case 0x17: /* Core 2 Extreme, Xeon, model 23*/
                msr = rdmsr(MSR_FSB_FREQ);
                bus = (msr >> 0) & 0x7;
                switch (bus) {
@@ -166,6 +155,16 @@
                        goto print_msr;
                }
                break;
+       case 0x1e:
+               /*
+                * XXX
+                * Newer CPUs will GP when attemping to access MSR_FSB_FREQ.
+                * In the long-term, use ACPI instead of all this.
+                */
+               aprint_debug("%s: unable to determine bus speed",
+                   device_xname(ci->ci_dev));
+               goto print_msr;
+               break;
        case 0x1: /* Pentium Pro, model 1 */
        case 0x3: /* Pentium II, model 3 */
        case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */