reading invalid msr on core duo yonah

[Adam Hoka <adam.hoka%gmail.com@localhost>]

Hi,

On recent current, I have to use the following, is this ok to commit?
Also cpuctl should list the stepping. (or i just cant find it there)

Index: x86/coretemp.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/coretemp.c,v
retrieving revision 1.23
diff -u -r1.23 coretemp.c
--- x86/coretemp.c      4 Mar 2011 11:56:27 -0000       1.23
+++ x86/coretemp.c      18 Mar 2011 16:28:29 -0000
@@ -293,7 +293,7 @@
         * but only consider the interval [70, 100] C as valid.
         * It is not fully known which CPU models have the MSR.
         */
-       if (model == 0x0E) {
+       if (model == 0x0E && extmodel != 0) {
 
                msr = rdmsr(MSR_TEMPERATURE_TARGET);
                msr = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);


cpu0: Intel Pentium M (Yonah) (686-class), 1828.90 MHz, id 0x6ec
cpu0: features  0xbfe9fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features  0xbfe9fbff<PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX,FXSR,SSE>
cpu0: features  0xbfe9fbff<SSE2,SS,HTT,TM,SBF>
cpu0: features2 0xc1a9<SSE3,MONITOR,VMX,EST,TM2,xTPR,PDCM>
cpu0: features3 0x100000<XD>
cpu0: "Intel(R) Core(TM) Duo CPU      T2400  @ 1.83GHz"
cpu0: I-cache 32KB 64B/line 8-way, D-cache 32KB 64B/line 8-way
cpu0: L2 cache 2MB 64B/line 8-way
cpu0: ITLB 128 4KB entries 4-way, 2 4MB entries fully associative
cpu0: DTLB 128 4KB entries 4-way, 8 4MB entries 4-way
cpu0: Initial APIC ID 1
cpu0: Cluster/Package ID 0
cpu0: Core ID 1
cpu0: family 06 model 0e extfamily 00 extmodel 00


-- 
Adam Hoka <adam.hoka%gmail.com@localhost>