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x86/include/cacheinfo.h
While I'm checking Intel's document, I found some bugs in cacheinfo.h.
The file includes INTEL_CACHE_INFO macro. The values in the macro are
described in "Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64
and IA-32 Architectures Software Developer's Manual Vol. 2A."
For the entry of 0x0d, cai_linesize is wrong but the value is not
used in kernel if my understanding is correct.
For the entry of 0xeb, cai_totalsize is wrong and the value is used
for the page coloring. Does this bug cause a serious problem?
I'm sorry that I'm not familiar with x86 :(
Index: sys/arch/x86/include/cacheinfo.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/cacheinfo.h,v
retrieving revision 1.13
diff -u -r1.13 cacheinfo.h
--- sys/arch/x86/include/cacheinfo.h 4 Dec 2011 17:00:10 -0000 1.13
+++ sys/arch/x86/include/cacheinfo.h 17 Jul 2013 05:11:50 -0000
@@ -234,7 +234,7 @@
__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \
-__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \
__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \
@@ -299,7 +299,7 @@
__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0xeb, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
--
-----------------------------------------------
SAITOH Masanobu (msaitoh%execsw.org@localhost
msaitoh%netbsd.org@localhost)
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