Here goes the project under brainstorming.

NetBSD/m88k will be organized as follows;

    m88k/		M88000 processor common
       m88k/
          trap.c, pmap.c, vm_machdep.c, sys_machdep.c, locore.s, ... 
       include/

Target port dependency would be concentrated in peripheral device
complex and CMMU configuration.  Let's say two targets; luna88k and
mvme88k.

   luna88k/
       luna88k/
          cmmu.c        2CMMU per CPU, upto 4 sets of CPU/CMMU module.
          machdep.c     machine dependent including interrupt machinary.

   mvme88k/
       mvme88k/
          cmmu187.c	1CPU with 2CMMU, mostly identical to luna88k.
          cmmu188.c     configurable CPU/CMMU would complicate logics.
       dev/             should be sharable with mvme68k/dev.


The sketch work of possible luna88k interrupt dispatcher like follows.
The routine will be called with arg0 pointing m88k trapframe which is
built atop of USPACE (deep bottom of kernel stack).  NetBSD/m88k will
have no UADDR by the way.

void
interrupt(tf)
        struct trapframe *tf;
{
        unsigned cpu, bits, level;
        cpu = cpu_number();

        bits = *(u_int32_t *)(0x65000000 + (4 << cpu));
        ipn = bits >> 29; /* highest IP number which is requesting */

        switch (ipn) {
        case 7 /* NMI */:
#ifdef DDB
                dive into DDB w/ tf value.
                break;
#else
                dump register values and top of stack contents.
                then halt.
#endif
        case 6 /* hardclock */:
                /* acknowledge hardclock interrupt */
                *(volatile u_int32_t *)(0x63000000 + (4 << cpu)) = ~0;
                bic_psr(PSR_IND);
                if (bits & (1 << 23)) {
                        /* trapframe when clock interrupt was taken */
                        hardclock(tf);
                }
                break;
        case 1 /* inter processor interrupt */:
                ipi = *(u_int32_t *)(0x6b000000 + (4 << cpu));
                do_ipireq(ipi);
                break;
        default:
                bic_psr(PSR_IND);
                (*ihandler[ipn])(tf, ipn);
                break;
        }
}

Because master CPU is solely responsible and in charge to handle
device interrupts in luna88k design, it's unnecessary to take into
consider about reentant device drivers.  More sketch work will be
posted hopefully for encouragement to other m88k port efforts.

Tohru Nishimura