I received the white box sent from United States this afternoon.
Thank you so much, Allen.  I'm delightful to have blan'new 88100/88200
UMs at hand.

After random reading, I realiazed I have to learn more about the
processor, in specific, CMMU manipulation.  I started feeling as if
88100 and 88200 were designed independently, in princple and approach.

I noticed that the possible interferance bewteen m88k framework and
target hardware.  M88K architecture itself provides no IPL.  It has
only PSR_IND bit on PSR.  Device interrupt control detail belongs
solely to target hardware designers.  A sort of CSR is implemented as
ususal.  Prioritized interrupt handling is in control by particular
hardware design and software logic.  So it might be awkward to have
mapping of NetBSD kernel spl*() to target machinary. 

Another concern is cache/TLB manipulation of 'remote' processors.  As
control registers of 88200 are memory mmapped on kernel space, then
it's easy to accomplish manipulating 'remote CMMUs' by just W/Ring
particular address ranges which belongs to 'remote processor'.  To be
or not to be here is, IPI framework should be used for the purpose.
I have no concrate thought yet this moment. 

Tohru Nishimura