> > Invalidate
> > Writeback
> > Writeback+Invalidate
>
> Ok. We could just s/writeback/sync/ in the above for slightly more
> generic names, and still reflect common hardware organisation.

It's better idea to avoid rather confusing clean and flush.  Okey, let
me redefine cache primitive naming.

- Synchronize Dcache
	Make sure target address range synchronized with Dcache.
	Write-back cache requires an explicit operation in processor
	specific way, while write-thru cache runs noop by definition.

- Invalidate Dcache
	Discard Dcache contents which belongs to target address range from
	cache, if any.

- Synchronize+Invalidate Dcache
	Make sure target address range synchronized with Dcache, if any,
	then discard the copy in Dcache.

	Write-thru cache just runs Dcache invalidate this case.

- Invalidate Icache
	Discard insns which were fetched from the target address range, if any.

(I'd hope here someone coins handy abbreviations like TBIA or TBIS)
 
Here goes some scenario to run cache primitives;

- program text segment has been modified (for software controlled single step)
	Run "Synchronize Dcache" and "Invalidate Icache" to make sure the
	new insn will be fetched.

- page has been removed
	If the target page is for program text, run "Invalidate Icache".
	If the target page has data whose contents are to be written
	to memory (marked dirty), then run "Synchronize+Invalidate Dcache".
	If the target page has data to be just discarded, then
	run "Invalidate Dcache".

- DMA read/write
	If DMA is a pullup from device, the target memory range must get
	invalidated with "Invalidate Dcache" for DMA.  If DMA is a
	push down to device, the cache contents must be written to target
	range with "Synchronize(+Invalidate) Dcache" for DMA.

void	
_bus_dmamap_sync(t, map, off, len, ops)
{
    ... IF write-back cache ...
	if (ops & BUS_DMASYNC_PREWRITE)
		Synchronize+Invalidate Dcache
	else if (ops & BUS_DMASYNC_POSTREAD)
		Invalidate Dcache

    ... IF write-thru cache ...
	if (ops & BUS_DMASYNC_POSTREAD)
		Invalidate Dcache

    ... IF the target port has dual cache personality, say, depending CPU
	models cache is either of write-thru or write-back, then these cache
	primitives would be pointers to ops determined on run time ...

	if (ops & BUS_DMASYNC_PREWRITE)
		(* Synchronize+Invalidate) Dcache
	else if (ops & BUS_DMASYNC_POSTREAD)
		(* Invalidate) Dcache
}

Tohru Nishimura
Nara Institute of Science and Technology