> > If we used true DMA, I'd agree. But aren't we doing pseudo DMA?
> > Thus all data went through the CPU, so the cache should have
> > seen Process B get paged in, as the CPU did it?
> 
> Hmm...  You are right...  The memory would have to go through the CPU
> to the physical addresses.  I'm not sure when it's necessary to flush
> the cache, now...

Yep, that's exactly what's been puzzling me for more than a year...

> > Also, how is the cache told not to cache IO addresses?
> 
> By bits in the page table.  There are "cache mode" bits and these are
> set to "cache-inhibit" for the I/O space (see pmap_bootstrap.c).

That's the case for the primary (on-chip) cache, right?  But, the
secondary (external) cache on accelerators has to have a priori
knowledge of cacheable and uncacheable space of given architecture,
don't they?

ken