> 
> On Jun 1,  1:45am, Jaime Kikpole wrote:
> >      I bring this up because I'm using 3 chip SIMMs and the other IIx has
> >2 chip SIMMs in it.  Do you think this would effect it?  I always assumed
> >not, but I'm not finding other problems.
> 
> Yup, that would be a problem.  What happened is that the II/IIx were
> designed before the design of 4MB SIMMs was finalized, and they guessed
> wrong on how many rows of refresh it would take.  So anything with 4Mbit
> chips (4MB = 8x4x1, 1MB = 2x1x4) or larger, needs a PAL to work in these
> machines.

You're right that the II and IIx were before the 4MB DRAMs were
finalized, but the problem I've heard was not a refresh one. It was
that the 4 MB chips added a self-test mode, which is activated if
you assert write while doing a memory refresh. As these computers
don't care about it, if the CPU is writing to an I/O address while a
memory refresh is happening, the chips go into self-test mode. NOT
good if the CPU has already started to set up memory (and do things
like make subroutine calls).

If you're still getting the tune followed by the chord, then you
have memory/hardware problems. Forget about a HD or a floppy.
Fix the memory first.

Parity SIMMS will work in Mac's. They just won't do anything more
than non-parity SIMMs.

Good luck!

Take care,

Bill