At 5:19 Uhr +0200 07.08.1997, Steven N. Hirsch wrote:
>On Wed, 6 Aug 1997, Bill Studenmund wrote:
>> The reason is that after the II came out (and evidently the IIx), the 4 MB
>> DRAM spec was changed to have a write durring a refresh cycle initiate
>> an on-chip memory test. The II didn't take this into account, and the Cpu
>> could write to I/O memory while the memory controller refreshed, initiating
>> a selftest after boot. Quite nasty. The PAL contains circuitry to make sure
>> all refresh cycles look like reads to the chips.
>
>Interesting.  Does this apply to use of 4 MB 30-pin SIMMs in an SE/30?  I
>would love to upgrade mine, but heard rumours that "standard" 4Mx8 modules
>didn't work.  If special SIMMs _are_ needed, who carries such a thing?

My SE/30 ran happily with vanilla 4Mx9 simms for a long time. AFAIK the
SE/30 came out at the same time as the IIcx. Due to its two memory banks
you can actually fill it up with 128 MB -- if you can afford it.

	hauke



--
"It's never straight up and down"     (DEVO)