> I haven't gotten around to looking at this yet, but I think the problem is
> that the level 4 interrupt handler is special-cased (for better serial
> performance maybe?) and doesn't process soft interrupts afterwards like
> the other interrupt handlers do. In (most?) other Macs, only the serial
> chip is at level 4, but on the AVs, the ethernet is there too. So... it
> looks like after ether_input() posts its softnet interrupt, it doesn't get
> handled until the next clock tick, which might be up to 17ms later.
> 
> Anybody (Bill Studenmund?) know why lev4intr just does an rte instead of
> jra rei like the other handlers?

No clue. What happens if you stick in a jra _ASM_LABEL(rei)?

Take care,

Bill