At 5:11 Uhr +0200 21.06.1998, Bruce Anderson wrote:
>On Sun, Jun 14, 1998 2:20 PM, Hauke Fath
><mailto:hauke@Espresso.Rhein-Neckar.DE> wrote:
>> At 8:54 Uhr +0200 12.06.1998, Vincent BARAT wrote:
>> >Bruce Anderson wrote:
>> >>
>> >> Your Centris 650 has a 16MHz I/O bus and no L2 cache.
>> >> compair that with a 486 mother board I have laying about
>> >>  64-256K L2 and I/O bus speed of 16 to 50MHz.
>>
>> Not quite. The NuBus, if you are referring to that, is a 32Bit wide
>
>I was  referring to the I/O bus.
>(See <A HREF="http://developer.apple.com/techpubs/hardware/
>Developer_Notes/Macintosh_CPUs-68K_Desktop/
>Mac_Centris_Quadra_800.pdf">Quadra 800</A>
>Chapter 2: "Architecture" page 14 (page 26 of 96) paragraph three.)

Ah, yes. I stand corrected. I have actually come across that, too, in the
meantime (searching for information on the floppy controller issue).

But still, this is no worse than the "Industry Standard Architecture": An
average i386 or i486 machine does all IO via the extension bus(ses), with
the exception of maybe serial/parallel IO and floppy access. IDE is a 16
bit wide bus clocked with 8MHz (essentially buffered ISA), and your AHA1542
sees the same bus bandwidth. Thngs may look a little different if you run a
VLB EIDE or SCSI controller, or with "newer" PCI based boards.

	hauke


--
"It's never straight up and down"     (DEVO)