On Mon, 3 Jun 2002, Nyef wrote:

> > 1.  The two modes of SWIM are IWM and ISM, not IWM and SWIM.
> 
> Okay. I just called it SWIM mode because it was new to the SWIM chip and
> none of the documentation I could find even _mentioned_ a mode switch.

Heh.  Well, the chip isn't exactly documented....


> > 2.  Yes, HDSEL can be set in either place.  You should probably control it
> > on the chip where possible, despite what classic Mac OS does.
> 
> Huh. I'd have thought that it would depend on the way the hardware is set
> up. Is this a wired-OR setup?

Not sure.  Don't have a wiring diagram.  (Well, I probably do, but I don't
care that much. ;-)  To be safe, set it in both places.


> > 4.  Need delays between accesses to the ISM cell.  Mental note: check
> > and probably fix this in the MkLinux/Darwin source.  :-)
> 
> Could you elaborate on this please?

I believe that the lack of this delay is the reason that the SWIM III
driver for MkLinux/Darwin wedges the SWIM chip every so often.  :-)

It probably isn't as big an issue on 68k, given the CPU speed, but it'd be
a real nightmare if the macppc folks try to support any SWIM II-based
machines and aren't expecting this.

I did the math in my head, and the delay should be either half a usec or a
usec.  Try 2 usec just to be safe, e.g. delay(2).  That's between any two
places where you touch any register on the chip, including switching
between IWM and ISM mode (if you even use IWM mode).  I'm actually going
to do 10 usec in the MkLinux/Darwin driver because I don't trust my math.

You should really do GCR in ISM mode, BTW, not in IWM mode.  It saves the
overhead and general clumsiness of doing a mode switch while probing a
newly-inserted disk.  Also, you'll have to do it in ISM mode when you try
to add support for the SWIM II.  Might as well get it over with.

The SWIM III code documents how to turn off the trans-space machine (MFM
encoder)  and how to do the GCR decoding and encoding in software.  The
only thing you'll have to figure out is how to set up the cell clock, and
you pretty much have to figure that out anyway, I think.


> > 5.  Register glitches:
> >
> > -ALL- registers are read/write (at least on SWIM and I think SWIM II).
> > Some have different values when reading.  The first few registers are
> > identical to SWIM III except the addition of the CRC functionality when
> > you write to the rError register.
> >
> > 0x1000 and up do not exist except on the SWIM III.  You might be seeing
> > mirrors caused by non-connected address lines....
> 
> I was thinking that the read/write select was dependant on that address
> bit for the SWIM I.

Don't know.  I thought you could treat it just like the bottom half of a
SWIM III, but I may be completely wrong.  If the 9 code treats them
differently, then trust the 9 code and ignore me.  :-)


Later,
David

---------------------------------------------------------------------
David A. Gatwood                                dgatwood@gatwood.net
Developer Docs Writer                             dgatwood@apple.com
Apple Computer                                  dgatwood@mklinux.org

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