>> trap type 200 at 30fc10
>
>Ouch.  That's a "machine check" trap and might happen for one of a
>couple of different reasons.

we've seen similar problems with the 7451, which led to Cliff's post: 
http://mail-index.netbsd.org/port-macppc/2001/12/14/0005.html

perhaps 7455s (the 1Ghz part) have a similar issue?

here's what we found with hacked in dumps of SRR1/MSSSR0:
>Dec 12 16:32:27 ox /netbsd: trap type 200 at 20c014 SRR1 0x149030
>Dec 12 16:32:27 ox /netbsd:  MSSSR0 0x1000
>Dec 12 16:32:27 ox /netbsd: panic: trap

SRR1 has bits 11 & 13 set. From MOTO's 7451 info:
>11 	MSS error.	Set for an L2 cache tag parity or L2 data parity
error. 
>			Also set for an L3 SRAM or L3 tag parity error;
otherwise
>			zero. [...]
>13 	TEA.		Set when TEA signal is asserted; otherwise zero

MSSSR0 looks like:
0x1000 == 00000000000000000001000000000000 ->bit 19 is set:
>19 	TEA 	Bus transfer error acknowledge
>			0 TEA not detected as asserted.
>			1 TEA detected as asserted.

>from 4.6.2:
>A TEA indication on the bus can result from any load or store operation 
>initiated by the processor. In general, TEA is expected to be used by a 
>memory controller to indicate that a memory parity error or an
uncorrectable 
>memory ECC error has occurred. Note that the resulting machine check 
>exception is imprecise and unordered with respect to the instruction that 
>originated the bus operation.

>9.4.3.3 Data Transfer Termination Due to a Bus Error
>The TEA signal indicates that a bus error has occurred during a data
tenure. 
>[...]
>For this reason, care must be taken to check for the end of physical memory

>and the location of certain system facilities to avoid memory accesses that

>result in the assertion of TEA.

HTH,
-mark