Hello,

> > Figure out the cache's size and clock ratio, then add something like this to your kernel config ( and config, make depend, make... )
> > options         L2CR_CONFIG="(L2SIZ_1M|L2CLK_20|L2RAM_PIPELINE_BURST)"
> > This is what I did for my 300MHz G3 with 1MB cache at 150MHz, so clock ratio is 2, there are other macros for different sizes...
> 
> > #define    L2SIZ_1M               0x30000000
> ok, mine has 1M
> 
> > #define    L2CLK_20               0x08000000 /*            / 2   */
> and runs the L2 cache at 200Mhz
1/2 the CPU speed - same ratio as mine.

> > ... and types...
> > #define    L2RAM_FLOWTHRU_BURST   0x00000000
> > #define    L2RAM_PIPELINE_BURST   0x01000000
> > #define    L2RAM_PIPELINE_LATE    0x01800000
> 
> where do i find data on which of these my cache does?  so far, i haven't
> found anything.

Then you almost certainly have pipeline burst cache and can use the same flags as I did.
( as always - keep a working kernel within reach in case things get wonky )

have fun
Michael