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Hello,

> > > the kernel was compiled with optimization flags (-maltivec is
included
> > > just by using the option above) and reports the cpu as:
> > >
> > > cpu0 at mainbus0: 7400 (Revision 2.7), ID 0 (primary)
> > > cpu0: HID0 8294c0a4<EMCP,ECLK,DOZE,DPM,EIEC,ICE,DCE,SGE,BTIC,BHT>
> > > cpu0: 409.10 MHz, no-parity 1MB WB L2 cache (PB SRAM) at 2:1 ratio
> >=20
> > I'm still wondering why it probes as ~410MHz.
> me too, results with the powerlogix software deviate +-1 mhz...

I wouldn't worry about +/- 1MHz in the probed CPU clock, but what you
said earlier - 44MHz bus clock - doesn't make much sense at all. Either
the card is running bus and core asynchronously ( seems odd ), at a very
odd ratio ( seems even weirder ) or the software got something wrong.
I'd suspect the bus runs slightly over 50MHz and the core runs at 8x bus
clock.

> > > - I don't know if I have a backside cache. To be honest I don't
> > > even know exactly what a backside cache is. I thought it was
> > > essentially 1:2 cache on the cpu or the cpu doughterboard.
> >=20
> > You do and it essentially means 'cache on a separate bus' - as
> > opposed to 'cache between CPU and mainboard'.
>=20
>=20
> should I try to make a kernel with cache enable options but no
> backside?

Err, how would you do that?

> could that be useful? From what you say I gather it would be stupid,
> since I have to set up the correct type of cache.

Does your utility say anything about cache RAM type? It's probably not
pipelined burst.

> > > - powerlogix states that speculative addressing could be a problem
> > > on non-g3/g4 computers which get such a processor. But My question
> > > is "why" ?
> >=20
> > No idea, I think it's enables here. ( Phase5 G3 card though )
> > See arch/powerpc/oea/cpu_subr.c for more flags to play with.
>=20
> the question is if you or other 604/604e (not ev) owners have that
> enabled when they upgraded to g3/g4.

I have it enabled as far as I can tell ( the cache utility says it's on,
no idea if it's on when NetBSD boots though )

> > Are there any switches on the card?
>=20
> I didn't see any.

Hmm, I wonder how the card gets configured then. Either it has some sort
of NVRAM to store some options set by a MacOS utility or it comes up in
some sort of safe mode and relies on some MacOS extension to set it up
properly.=20

> > > the powerlogic utility reports the L2CR bytesin hex that it will
> > > use.
> > > Could it be useful to get those? netbsd should come up with the
> > > same values?
> >=20
> > Most definitely and yes I think so. It would at least tell us what
> > MacOS uses.
>=20
> 0xB9080000
>=20
> I wonder to what netbsd sets them with my settings...

Let's see...
#define	  L2CR_L2E		  0x80000000 /* 0: L2 enable */
#define	   L2SIZ_1M		  0x30000000
#define	   L2CLK_20		  0x08000000 /*            / 2   */
#define	   L2RAM_PIPELINE_BURST	  0x01000000
#define	  L2CR_L2WT		  0x00080000 /* 12: L2 write-through. */

So pipeline burst is what MacOS uses too, but you may want to add
L2CR_L2WT.

> ah I compiled another kernel (very tedious, I need to boot your old
> 2.99 kernel, of which I don't have the configuration, which is slow=20
> of course had has broken mc0)

You can extract the config file from the kernel image, although I forgot
how exactly ( wasn't quite trivial as far as I remember )

> specifying -mcpu-7400 and -O3 in mk.conf
> (instead of passing them on the command line)
> 	- the kernel is smaller than my previous one
> 	- X11 works with the standard X server and has no color
>          bandings!

Nice :)

> 	- it seem a tad more stable, but the ssytem freezed after a cvs
> update, a bit of compile and X usage.

Maybe putting the cache into write-through mode helps.

> 	- ppc kernels freeze in X just freeze, like good ol' mac! they
> don't drop back into console like sparcs.

That's XFree's fault and has nothing to do with the kernel. A sparc
running XFree won't drop back to the console on panic either.

have fun
Michael

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