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Re: Show stopper bugs for 5.0
On Tue, May 20, 2008 at 08:39:09PM -0400, Michael Lorenz wrote:
> I didn't commit the fix yet because chuq thinks that's just a
> workaround for a problem elsewhere, but I couldn't find anything
> remotely related in the 7400 errata list. He's got a dual 7455 which
> doesn't have this problem - his CPUs have L3 cache though, no idea if
Maybe it's L1 cache have different characteristics ?
Could it happen that this part of code has already been cached in your
L1 instruction cache at this point of operations, but not on chuq's ?
--
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
NetBSD: 26 ans d'experience feront toujours la difference
--
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