Re: severely bad timekeeping

[Havard Eidnes <he%NetBSD.org@localhost>]

> > In passing, what would I need to do to figure out what L2CR_CONFIG
> > settings I want for this CPU?  "L2 cache present but not enabled"
> > sounds like a performance killer, and the macppc FAQ points to list
> > mail indicating that setting L2CR_CONFIG is the right magic, but
> > doesn't give much guidance on what to set it to.
>
> It definitely kills performance.
> You'll need to find out what size your cache is - 1MB at 1/2 CPU clock  
> is very common with 300MHz upgrades.

To be concrete, the possible values to use for L2CR_CONFIG can be
found in sys/arch/powerpc/include/spr.h, under SPR_L2CR.

These are used by sys/arch/powerpc/oea/cpu_subr.c.

I have an Apple MacIntosh 7600 which has gone through two CPU upgrades
in it's lifetime, from 133MHz 604 to 350MHz G3 to 1GHz G4.  Of course
OFW is unchanged at 1.0.5, so it doesn't know how to configure those
newer CPUs.  In both those cases I've therefore had to provide the CPU
config in the kernel config file.

In my cases the 350 MHz G3 had 1MB L2 cache at 1/2 speed with
"pipeline burst" memory, while the 1GHz G4 has a 256KB L2 cache at
full speed, and a 2M L3 "pipeline burst 2" SRAM cache at 1/4 speed.
So for each of them, I had, respectively:

# Enable & config 1M cache on 1/2 speed on G3 350MHz board
options         L2CR_CONFIG="(L2SIZ_1M|L2CLK_20|L2RAM_PIPELINE_BURST)"

and

# Enable & config 2M L3 cache at 1/4 speed & 256K L2 cache 1/1 speed
# on G4 1000MHz board
options         L2CR_CONFIG="(L2CR_L2E)"
options         L3CR_CONFIG="(L3SIZ_2M|L3CLK_40|L3CKSP_4|L3RT_PB2_SRAM)"

added to my kernel configs.

As you'll see from the spr.h header file, you really need to know the
exact characteristics of your CPU in order to ensure that the CPU
config is correctly set in the config file. 

Hope this helps.

Best regards,

- Håvard