7600+G3 cache

[der Mouse <mouse%Rodents-Montreal.ORG@localhost>]

That 7600 with a G3 card I've been trying to get the cache enabled on
is giving me trouble.

I've been trying different L2CR_CONFIG settings.  They've all been
L2SIZ_512K and L2CLK_20, the former because the CPU card is marked
"300/512" and is running at close enough to 300MHz that I believe the
300 is the clock speed and the 512 is the cache size.  But after trying
all three L2CR_L2RAM values, I'm a bit baffled.

With L2RAM_FLOWTHRU_BURST, I get:

avail memory = 88328 KB
timecounter: Timecounters tick every 10.000 msec
found Grand Central at 0xf3000000
mainbus0 (root)
cpu0 at mainbus0: 750 (Revision 2.2), ID 0 (primary)
cpu0: HID0 8090c0a4<EMCP,DOZE,DPM,ICE,DCE,SGE,BTIC,BHT>, powersave: 1
cpu0: 305.89 MHz, no-parity 512KB WB L2 cache (FB SRAM) at 2:1 ratio
ppppppppppppptttttttttttttttttttttttptppppppppppppppppppppptptttpttpttptttttttttttpttpppppppppptpppptppptppppttptttttptttpttpttppttpptpttptpttpppppptpttpttpttpttpttpttpttttttppttpppttpttppppttptpptpptptttpttptttttpttpttpppttpppttttttttttttttttttppppppppppppppppppppppttttttttpppppppptppptppppptttptttttttttpttpttpttppptpttptppptppptppptpttpppttpttpttptttpttptttttptpttpppppppppppppptttttttttttttttttttttttppppppppptttttttttttttttttttttttpppppppppppppppppppppptptpttppppttpttpttpttpttpttpttttpttpttpttppptpppptpppppptppptptttpttptttttptttptpptttppppppppttptppttptppttptttppptpppppttptpppptptpppttpttpttppppttpptttttttpppttpttpttptpppptpppppttpppttpptptttptppppttpptpttppptttptptttptppptttpppttpppppttpttppptpptttppptpttpptptptptpptttptpttttttttttttttttttttttttttttttttttttttttttttttttttttttttttpttttttppttttttttttttttpttptttttttttttttpttttttttttttttttttptttttpttpppttptttpttpptttttptttpptttptttppttpttttttttttptttttpttttptttptppptttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt
 t!
ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttptptttptpptpttptptptttpptpttptpptttttttrap:
 pid 0.0 (): kernel PGM trap @ 0x4130a00 (SRR1=0x80030)
panic: trap
Stopped at

So I think that's not right.

With L2RAM_PIPELINE_BURST, I get the same "L2 cache present but not
enabled" report that I do with no L2CR_CONFIG at all.  (This puzzles
me, and I'm fairly sure I was indeed using the correct kernel.)

With L2RAM_PIPELINE_LATE, I get

avail memory = 88328 KB
timecounter: Timecounters tick every 10.000 msec
found Grand Central at 0xf3000000
mainbus0 (root)
cpu0 at mainbus0: 750 (Revision 2.2), ID 0 (primary)
cpu0: HID0 8090c0a4<EMCP,DOZE,DPM,ICE,DCE,SGE,BTIC,BHT>, powersave: 1
cpu0: 305.89 MHz, no-parity 512KB WB L2 cache (LW SRAM) at 2:1 ratio
trap: kernel ISI by 0x7e4802a4 (SRR1 0x10003030), lr: 0xff80f278
panic: trap
Stopped at

This leaves me wondering what's wrong.  Could it maybe be write-through
instead of write-back?  Maybe I need to turn on parity enable?

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