Re: zs serial and interrupt sensitivity

[David Riley <fraveydank%gmail.com@localhost>]

On May 3, 2011, at 11:29 PM, Wim Lewis wrote:

> On 5/3/11 12:39 PM, David Riley wrote:
>> Switching the interrupts to level sensitive seems to have fixed my problems. 
>>  Can anyone think of a good reason this should be edge-sensitive?
> 
> As I understand the Zilog interrupt system, the interrupt acknowledge
> cycle should always bring /INT high again at least for a while, so an
> edge-triggered interrupt should work. On the other hand, if /INT is
> asserted, that means there definitely is a pending interrupt that needs
> servicing... so making it level triggered should be more robust. :)

If that's the case, you almost certainly want level triggered; edge triggered 
interrupts are for devices which only send a short pulse out, usually negating 
before you even get to the acknowledge.  If you've gotten to the acknowledge 
already, you're processing it, so it doesn't matter what state the line is in.

The interrupt acknowledge negating the interrupt is a pretty normal thing; the 
expectation is that when you do an interrupt acknowledge, you're getting the 
information about all the pending interrupts right then and there, so it can 
release the IRQ pin.  If another event happens during the processing of the 
handler, the pin will reassert itself, and the interrupt should fire again.  
Unfortunately, some interrupt controllers don't handle that scenario well if 
it's edge-triggered and ignore the asserted line, since they expect the source 
to only fire pulses.

> I don't know how the z8530 is connected to the rest of the interrupt
> system on a macppc system, though; this is just my understanding of the
> z8530 itself. Glancing through the zs driver code I can't even tell if
> it's doing hardware or software INTACKs.

It probably shouldn't matter, but given that genuine software INTACKs aren't 
available until the CMOS version (which came along midway through the 68k 
line), I wouldn't be surprised if the original code used hardware INTACKs with 
one of the address lines as the #INTACK line (the 68K had real interrupt 
acknowledge cycles, but they were probably not mapped directly to the 8530; I 
could be wrong about that).

- Dave