On Tue, 26 May 1998 11:36:25 -0400 
 Matt Thomas <matt@3am-software.com> wrote:

 > fta0 at tc0 slot 0 offset 0x0: DEC DEFTA TC FDDI SAS Controller 
 > fta0: FDDI address 08:00:2b:a0:1f:0d, FW=0.7a, HW=2, SMT V7.2 
 > fta0: FDDI Port = S (PMD = ANSI Single-Mode Type 1) 

Cool!  :-)

 > Ping times are horrible (considering the ENTIRE cache is flushed
 > multiple times for transmit and receive).  But it does run.

Ok, I just rewrote _bus_dmamap_sync() for the R3000 case, now that
I have a better grip on how the caches work on the R3000 and R4000.

Amusingly, my MIPS architecture manual says that the R{2,3}000 cache
is _write-though_, so I am wondering why flushes are even necessary.
Can someone enlighten me here?

The R4000 case still needs some work, which I'll try and do this week; some
data structure changes are going to be needed.  (mmm, virtually-indexed
caches, gag.)

Please try it with the lastest version of pmax/bus_dma.c (1.2).

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                            Home: +1 408 866 1912
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