Subject: Re: R4000 cache lines
To: Michael L. Hitch <mhitch@lightning.oscs.montana.edu>
From: Jason Thorpe <thorpej@nas.nasa.gov>
List: port-mips
Date: 06/03/1998 10:28:54
On Wed, 3 Jun 1998 10:17:22 -0600
mhitch@lightning.oscs.montana.edu (Michael L. Hitch) wrote:
> I was going to ask if there would ever be a userspace address. I don't
> know of any case where it might be - as far as I know, any I/O to userspace
> is done through kernel virtual addresses. The one case that will currently
> cause problems on the mips is if the address is on the kernel stack. The
> kernel stack is still being mapped at UADDR, and the mapping may change
> between process context switches.
There isn't currently anything that does DMA directly to a user space
address, but the bus_dma specification _allows_ it (and in my paper for
USENIX, I provide an example of how it might be used).
> The only problem I see with Jason's change is the same problem I have with
> some of the cache flushing in pmap: it flushes all the entries within the
> virtually-indexed range. This could be flushing entries containing
> different physical addresses/tags, which is not necessary. I don't see
> any easy way around that though.
Yah, sigh. But, what to do about flushing for user space addresses for
non-curproc? Grovel the pmap's software page tables and look into the
cache registers?
Jason R. Thorpe thorpej@nas.nasa.gov
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