Toru Nishimura and I would like to merge the mips work which 
we've done back into the main tree.  We're detailing the changes here
so people can provide feedback, but we'd really like to get these
changes in well before the 1.4 branch so people can try testing
systems with them beforehand.  Suggestions for improved solutions
are welcome, particularly if accompanied by code.

We're shooting for checking things in next week, so things may be a little
shaky for a while.

There will be code on cvs.netbsd.org:~castor/mips-0107.tgz which 
demonstrates the changes but there are a few glitches that will
be removed as we commit stuff. (Namely, we will likely not remove 
include/regdef.h and friends, since that will break other people's mips code,
and things will probably be put back to use them and avoid duplicating
the code in cpuarch.h, the memcpy.S in lib/libkern got contaminated by
some mips3 instructions.  I'm sure there are others.)

Summary of changes:

* Support for 64-bit safe user code
    Affected Files:
	${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp* 
	include/setjmp.h mips/include/[lots] mips/mips/[lots]

    Solution:

	We define macros REG_L/REG_S and SZREG for loading and storing
	registers and for the size of registers.  The exact meaning
	of these is controlled by a macro (currently _MIPS64) which
	allows one to treat the registers as either 32-bit or 64-bit.
	There are data types mips_reg_t and mips_fpreg_t which represent
	the true register sizes, and avoid confusing register_t.

	We needed a way to dynamically gen the structure sizes of things
	like sigcontext for setjmp.h, so we defined a pubassym.cf for
	libc routines like setjmp and longjmp.
    
	NetBSD/mips allows ${ARCH}'s to be defined which preserve 
	all 64-bits of registers across user context switches.  There
	are still a few niceties to clean up for kernel mode context
	switches.

* Support for QED 52xx processors
    Affected Files:
	mips/locore_mips3.S mips/pmap.c include/locore.h
    
    Issue:
	The QED 52xx family of processors are targeted at low cost
	embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
	etc.  We have added preliminary support for some of the idiosyncrasies
	of this processor, e.g. no L2 cache, etc.  More work needs to be
	done here because with a modest 2-way  L1 cache, some of the rampant
	flushing has significant performance implications.  However, 
	it doesn't crash, which is a start.

    Solution:
	A routine for flushing the cache based on virtual addresses was added;
	a routine which deals with the two-way set associativity of the
	5230 L1 cache was added, accomodations to 5230's instruction hazards
	were added.
	

* TLB Miss code for mips3/mips4 processors cleaned up significantly.
    Affected Files:
	mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
    Issue:
	The TLB Miss handler exceeded the allowed size, which wasn't 
	a problem because there was no handler for when the processor
	was in 64-bit mode.  The handler for invalid TLB exceptions
	also appears to have much vestigial code, which made it 
	difficult to understand.

    Solution:
	Use the XCONTEXT register to store a pointer to the segment
	map table, this coupled with removing some dead code allows
	the handlers to fit.

* Elimination of UADDR/KERNELSTACK constants

   Affected files:
	include/mips_param.h, include/pcb.h,
	mips/locore_mips1.S, mips/locore_mips3.S,
	mips/mips_machdep.c, mips/vm_machdep.c

   Issue:
	NetBSD/mips currently uses a fixed-address kernel stack.  The
	USPACE (two 4KB pages) of each process has two distinct KSEG2
	addresses, both refer to a single physical region; one address
	for fixed range [ UADDR .. KERNELSTACK ), and another for
	"normal" KSEG2 address of USPACE which was allocated by kernel
	memory manager and unique to each of USPACEs.

	The "Doubly mapped" USPACE complicates context switching.  Both
	address ranges have to be managed with a special care for
	"wired" TLB entries which are never replaced until next context
	switch in order to ensure no TLB miss on USPACE accesses.  It also
	potentially thrashes the MIPS processor cache since the caches
	are virtually indexed.

   Solution:

	Purge KERNELSTACK constant for kernel stack pointer.  Context
	switch is now simplified as it unloads half of TLB hardwiring
	burden.  It just manages the unique KSEG2 address of each
	USPACE to be wired.  As the side effect, switch_exit() has no
	MIPS processor ISA dependent code anymore.  It now just switchs
	kernel stack to proc0's USPACE which has a KSEG0 address and no
	wired TLB entries.

* Extensive use of 'genassym.cf'

To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects.  This change will contribute possible NetBSD/mips64
portability too.

* Changes in kernel mode exception handlers

Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack in order to resume kernel mode
processing.  This context is now represented with 'struct trapframe'
and pointed by trap()'s 5th argument.

* Refurblished DDB backtrace routine

It's a growing concern to maintain stacktrace() code correctly.  It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.

New backtrace code searchs for certain instructions peculiar to any of
function tails.  Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.

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