Takao Shinohara <shin@sm.sony.co.jp> writes:
> 
> I think I found the cause of the core-dump problem.
> 
> In function mips3_FlushDCache(), secondary cache is flushed by virtual
> address. But we need physical address to flush secondary cache
> properly.

Simon, could you test this patch?

I can't test it myself, because I have no R4000/R4400 machine with
secondary cache.

Takao Shinohara

patch summary:

    change mips3_FlushDCache()	flush primary cache only
    add mips3_FlushDCachePA()	flush secondary cache by phisical addr
    change pmap_enter_pv()	call mips3_FlushDCachePA() if secondary
				cache is present

--- include/locore.h.org	Sat Sep 25 09:00:37 1999
+++ include/locore.h	Wed Nov  3 09:49:54 1999
@@ -72,11 +72,12 @@
 
 extern void mips3_ConfigCache __P((void));
 extern void mips3_FlushCache  __P((void));
-extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len));
+extern void mips3_FlushDCache __P((vaddr_t addr, vsize_t len));
+extern void mips3_FlushDCachePA __P((paddr_t addr, vsize_t len));
 #ifdef	MIPS3_L2CACHE_ABSENT
-extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len));
+extern void mips52xx_FlushDCache __P((vaddr_t addr, vsize_t len));
 #endif
-extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len));
+extern void mips3_FlushICache __P((vaddr_t addr, vsize_t len));
 extern void mips3_ForceCacheUpdate __P((void));
 extern void mips3_HitFlushDCache __P((vaddr_t, int));
 extern void mips3_SetPID  __P((int pid));
--- mips/pmap.c.org	Wed Nov  3 09:43:01 1999
+++ mips/pmap.c	Wed Nov  3 10:02:57 1999
@@ -1909,6 +1909,9 @@
 					    != (va & mips_CacheAliasMask)) {
 						pmap_page_cache(pa,PV_UNCACHED);
 						MachFlushDCache(pv->pv_va, PAGE_SIZE);
+#if !defined(MIPS3_L2CACHE_ABSENT)
+						mips3_FlushDCachePA(pa, PAGE_SIZE);
+#endif
 						*npte = (*npte & ~MIPS3_PG_CACHEMODE) | MIPS3_PG_UNCACHED;
 #ifdef DEBUG
 						enter_stats.ci++;
--- mips/locore_mips3.S.org	Sat Oct 30 22:12:20 1999
+++ mips/locore_mips3.S	Wed Nov  3 10:27:21 1999
@@ -1734,10 +1734,9 @@
 LEAF(mips3_FlushDCache)
 	lw	a2, mips_L1DCacheSize
 	addiu	a2, -1
-	move	t0, a0		# copy start address
 	and	a0, a0, a2	# get index into primary cache
 	addu	a1, 127		# Align
-	li	a2, 0x80000000
+	li	a2, MIPS_KSEG0_START
 	addu	a0, a0, a2
 	addu	a1, a1, a0
 	and	a0, a0, -128
@@ -1745,7 +1744,7 @@
 	srl	a1, a1, 7	# Compute number of cache lines
 	move	t1, a1		# copy length
 1:
-	cache	1, 0(a0)
+	cache	1, 0(a0)	# Index_WriteBack_Invalidate_D
 	cache	1, 16(a0)
 	cache	1, 32(a0)
 	cache	1, 48(a0)
@@ -1757,28 +1756,47 @@
 	bne	a1, zero, 1b
 	addu	a0, 128
 
-#if 1
-	lw	a2, mips_L2CacheSize
-	beq	a2, zero, 2f	# no secondary cache
-	addiu	a2, -1
-	and	t0,t0,a2	# secondary cache index
-	li	a0, 0x80000000
-	addu	a0, a0, t0	# reduce to kseg0 address
+	j	ra
+	nop
+END(mips3_FlushDCache)
+#endif
+
+/*----------------------------------------------------------------------------
+ *
+ * mips3_FlushDCachePA --
+ *
+ *	void mips3_FlushDCachePA(addr, len)
+ *		paddr_t addr; vsize_t len;
+ *
+ *	Flush secondary data cache for range of addr to addr + len - 1.
+ *
+ * Results:
+ *	None.
+ *
+ * Side effects:
+ *	The contents of the cache is written back to primary memory.
+ *	The cache line is invalidated.
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(mips3_FlushDCachePA)
+	lw	t0, mips_L2CacheSize
+	li	t1, MIPS_KSEG0_START
+	beq	t0, zero, 2f	# no secondary cache
+	addu	a0, a0, t1	# convert physical addr to kseg0 addr
 1:
-	cache	3, 0(a0)
+	cache	3, 0(a0)	# Index_WriteBack_Invalidate_SD
 	cache	3, 32(a0)
 	cache	3, 64(a0)
 	cache	3, 96(a0)
-	addu	t1, -1
-	bne	t1, zero, 1b
+	addu	a1, -128
+	bne	a1, zero, 1b
 	addu	a0, 128
 2:
-#endif
 
 	j	ra
 	nop
-END(mips3_FlushDCache)
-#endif
+END(mips3_FlushDCachePA)
 
 /*----------------------------------------------------------------------------
  *