[ ... Jeff Smith replied me about CP0 hazard ... ]

>> How many nop's are required given most 'hazardous' CP0 MIPS processors
>> to make the following work correctly?
>
> That code looks correct.  QED in the 52xx manual has done a good
> job of documenting things.

Here goes my understanding.   Feel free to correct me if wrong.

	.set	mips3
LEAF_NOPROFILE(mips3_TBIS)
	...
        dmtc0   a0, MIPS_COP_0_TLB_HI           # look for the vaddr & ASID
        nop
        nop
        tlbp                                    # probe the entry in question
	
Two nop's are required before issuing tlbp.

        tlbp                                    # probe the entry in question
        nop
        nop
        mfc0    v0, MIPS_COP_0_TLB_INDEX        # see what we got

I'm uncertain here whether two nop's are necessary to read TLBindex
register after tlbp.

        mfc0    v0, MIPS_COP_0_TLB_INDEX        # see what we got
        #nop                                    # -slip-
        #nop                                    # -slip-
        bltz    v0, 1f                          # index < 0 then skip

Nop's are unnecessary because "slip cycle" is inserted to prevent
register resource conflict (interlock).  Right?

        dmtc0   zero, MIPS_COP_0_TLB_LO1        # zero out entryLo1
        nop
        nop
        tlbwi

Two nop's are necessary before issuing tlbwi.

        tlbwi
        nop
        nop
1:
        dmtc0   t0, MIPS_COP_0_TLB_HI           # restore current ASID

Are these nop's necessary to have?

        dmtc0   t0, MIPS_COP_0_TLB_HI           # restore current ASID
        nop
        nop
        j       ra
        mtc0    v1, MIPS_COP_0_STATUS           # restore status register
        END(mips3_TBIS)

It's safer to have two nop's here to make sure ASID is restored before
return.  Correct?

Tohru Nishimura
Information Technology Centre
Nara Institute of Science and Technology