Subject: Re: -DSOFTFLOAT && -DNOFPU
To: None <port-mips@netbsd.org>
From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
List: port-mips
Date: 04/15/2000 14:51:57
Here goes the sketchy code segment. The issue is how to implement
lazy FP context scheme given no FP register MIPS processor.
case T_COP_UNUSABLE+T_USER:
if (cpuinfo.fpuirr != 0) {
savefpregs(fpcurproc);
loadfpregs(p);
}
fpcurproc = p;
if (cpuinfo.fpirr == 0)
dealfpu(status, cause, opc);
else {
struct frame *f = p->p_md.md_regs;
f->f_regs[SR] |= MIPS_SR_COP_1_BIT;
}
p->p_md.md_flags |= MDP_FPUSED;
userret(p, opc, sticks);
return; /* GEN */
case T_FPE+T_USER:
dealfpu(status, cause, opc);
userret(p, opc, sticks);
return; /* GEN */
where dealfpu() will handle CP1 load/store insns, too.
This change would overload the meaning of fpuirr value 0, which is now
meant no FP regs. It'd be rather nice to introduce -1 or something
special.
Tohru Nishimura