mhitch>   I've also alway thought there should be some cache invalidate
mhitch> operations for those cases where you don't need the cache 
mhitch> flushed to memory.

cgd> yeah, the pre-DMA ops could use this type of thing, certainly.

jeffs> That's is a win too.  The code has to be careful to avoid cache line
jeffs> tearing and invalidating outside the buffer.  IRIX does this.

Yeah, not only invalidation, but also solely write-back operation is
desirable, since BUS_DMASYNC_PREWRITE of bus_dmamap_sync(9) may get 
a benefit of it.

soren> Whoever does it should also keep Nisimura-san's recent suggestions
soren> in mind..

If I understand correctly, his proposal basically means having
following cache primitives:

	- invalidate instruction cache
	- invalidate data cache
	- writeback and invalidate data cache
		This is what our current FlushDCache() does.
		On MIPS1, this should be just same function with 
		invalidation, since MIPS1's cache is write-through,
	- writeback data cache
		On MIPS1, this should be just no operation,
		since MIPS1's cache is write-through,
--
soda