Subject: Re: more on understanding caches.
To: Chris G. Demetriou <cgd@sibyte.com>
From: Jeff Smith <jeffs@geocast.com>
List: port-mips
Date: 06/29/2000 13:03:58 
"Chris G. Demetriou" wrote:

>         * why does pmap_procwr() flush both I and D for >	>	    mips3, but only flush I for mips1?

My guess is that the R[23]000's caches are write thru, so
you don't have to sync it.

>         * most FlushDCache routines seem to use		>	    writeback-invalidate. the r3900 one seems
>	    to use invalidate (i.e., no write-back!).

Does the r3900 have a writethru cache?

jeffs