Toru Nishimura wrote:
> 
> >> Could it be possible for NetBSD to use the Mips 's CPU timer
> >> to call hardclock ?
> >
> > Yes, that's no problem.
> 
> A side note about how cpu_intr() is organized.
> 
> cpu_intr() is called with master interrupt MIPS_SR_INT_IE off.  This
> is (was) an artifact of R3000 'stacked interrupt mask', and
> locore_mips3.S simulates locore_mips1.S behaviour.  NetBSD/cobalt
> seems to handle all of HARD_INT requests leaving MIPS_SR_INT_IE off.
> I guess that's the reason why NetBSD/cobalt 'slips' clock severely
> when system load is high.

> I have been toying the idea that master interrupt MIPS_SR_INT_IE is
> kept on when cpu_intr() is called while HARD_INT bits in SR turned
> off.  Then, cpu_intr() can enable HART_INT bits (the effect like
> spllower) gradually, say, as you wish, to reflect interrupt priorities
> of devices.

The platform code can do this itself.  Our (internal) platform lowers
the spl to the appropriate spl before calling the isr.  Handling
SR_INT_IE is easy enough, but it would be a cleaner interface.

On this note, has anyone looked at updating the code to not just
plug zero in, so someday we can have KX on for 64b kernels?

jeffs