Folks,

I was puzzled a bit with exception return codes in locore_mips3.S

I think exception returns can be done in following steps,

	- restore SR value on exception time with mtc0 insn.
	- because it has EXL bit, MIPS3 processor now blocks interrupts
	  and enters critical section to restore the register values when
	  exception was taken.

Code paths found in locore_mips3.S are somehow inconsistent each
others and looks redundant.  I remember it used to be as simple as
mentioned above.  I wonder why they are done in such ways, and whether
it's possible to make locore_mips3.S simple.

Tohru Nishimura