This is far from the complete rototill that I want to undertake, but
this makes my SGI Indy (with 2-way cache R4600) get the correct cache
ops.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>

Index: include/locore.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/locore.h,v
retrieving revision 1.52
diff -c -r1.52 locore.h
*** include/locore.h	2000/10/31 23:39:24	1.52
--- include/locore.h	2001/06/11 19:11:16
***************
*** 67,75 ****
  
  void	mips3_ConfigCache(int);
  void	mips3_FlushCache(void);
! void	mips3_FlushDCache(vaddr_t addr, vaddr_t len);
! void	mips3_FlushICache(vaddr_t addr, vaddr_t len);
! void	mips3_HitFlushDCache(vaddr_t, int);
  
  void	mips3_SetPID(int pid);
  void	mips3_TBIA(int);
--- 67,75 ----
  
  void	mips3_ConfigCache(int);
  void	mips3_FlushCache(void);
! void	mips3_FlushDCache(vaddr_t addr, vsize_t len);
! void	mips3_FlushICache(vaddr_t addr, vsize_t len);
! void	mips3_HitFlushDCache(vaddr_t, vsize_t);
  
  void	mips3_SetPID(int pid);
  void	mips3_TBIA(int);
***************
*** 83,90 ****
  
  void	mips3_FlushCache_2way(void);
  void	mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len);
- void	mips3_HitFlushDCache_2way(vaddr_t, int);
  void	mips3_FlushICache_2way(vaddr_t addr, vaddr_t len);
  
  u_int32_t mips3_cp0_compare_read(void);
  void	mips3_cp0_compare_write(u_int32_t);
--- 83,90 ----
  
  void	mips3_FlushCache_2way(void);
  void	mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len);
  void	mips3_FlushICache_2way(vaddr_t addr, vaddr_t len);
+ void	mips3_HitFlushDCache_2way(vaddr_t, vsize_t);
  
  u_int32_t mips3_cp0_compare_read(void);
  void	mips3_cp0_compare_write(u_int32_t);
***************
*** 111,116 ****
--- 111,117 ----
  	void (*flushCache)(void);
  	void (*flushDCache)(vaddr_t addr, vsize_t len);
  	void (*flushICache)(vaddr_t addr, vsize_t len);
+ 	void (*hitflushDCache)(vaddr_t, vsize_t);
  	void (*setTLBpid)(int pid);
  	void (*TBIAP)(int);
  	void (*TBIS)(vaddr_t);
***************
*** 129,159 ****
  
  /*
   * The "active" locore-fuction vector, and
- 
   */
  extern mips_locore_jumpvec_t mips_locore_jumpvec;
  extern mips_locore_jumpvec_t r2000_locore_vec;
  extern mips_locore_jumpvec_t r4000_locore_vec;
  extern long *mips_locoresw[];
  
! #if defined(MIPS3) && !defined (MIPS1)
! #if	defined(MIPS3_5200)
! #define MachFlushCache		mips3_FlushCache_2way
! #define MachFlushDCache		mips3_FlushDCache_2way
! #define MachHitFlushDCache	mips3_HitFlushDCache_2way
! #define MachFlushICache		mips3_FlushICache_2way
! #else
! #define MachFlushCache		mips3_FlushCache
! #if	defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
! #define MachFlushDCache         mips3_FlushDCache		/* VR4100 */
! #elif	!defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
! #define MachFlushDCache		mips3_FlushDCache
! #else
  #define MachFlushDCache		(*(mips_locore_jumpvec.flushDCache))
! #endif
! #define MachHitFlushDCache	mips3_HitFlushDCache
! #define MachFlushICache		mips3_FlushICache
! #endif
  #define MachSetPID		mips3_SetPID
  #define MIPS_TBIAP()		mips3_TBIAP(mips_num_tlb_entries)
  #define MIPS_TBIS		mips3_TBIS
--- 130,151 ----
  
  /*
   * The "active" locore-fuction vector, and
   */
  extern mips_locore_jumpvec_t mips_locore_jumpvec;
  extern mips_locore_jumpvec_t r2000_locore_vec;
  extern mips_locore_jumpvec_t r4000_locore_vec;
  extern long *mips_locoresw[];
  
! /*
!  * Always indirect to get the cache ops.  There are just too many
!  * combinations to try and worry about.
!  */
! #define MachFlushCache		(*(mips_locore_jumpvec.flushCache))
  #define MachFlushDCache		(*(mips_locore_jumpvec.flushDCache))
! #define MachFlushICache		(*(mips_locore_jumpvec.flushICache))
! #define	MachHitFlushDCache	(*(mips_locore_jumpvec.hitflushDCache))
! 
! #if defined(MIPS3) && !defined(MIPS1)
  #define MachSetPID		mips3_SetPID
  #define MIPS_TBIAP()		mips3_TBIAP(mips_num_tlb_entries)
  #define MIPS_TBIS		mips3_TBIS
***************
*** 162,171 ****
  #define proc_trampoline		mips3_proc_trampoline
  #endif
  
! #if !defined(MIPS3) && defined (MIPS1)
! #define MachFlushCache		mips1_FlushCache
! #define MachFlushDCache		mips1_FlushDCache
! #define MachFlushICache		mips1_FlushICache
  #define MachSetPID		mips1_SetPID
  #define MIPS_TBIAP()		mips1_TBIAP(mips_num_tlb_entries)
  #define MIPS_TBIS		mips1_TBIS
--- 154,160 ----
  #define proc_trampoline		mips3_proc_trampoline
  #endif
  
! #if !defined(MIPS3) && defined(MIPS1)
  #define MachSetPID		mips1_SetPID
  #define MIPS_TBIAP()		mips1_TBIAP(mips_num_tlb_entries)
  #define MIPS_TBIS		mips1_TBIS
***************
*** 173,190 ****
  #define wbflush()		mips1_wbflush()
  #define proc_trampoline		mips1_proc_trampoline
  #endif
- 
- 
  
! #if defined(MIPS3) && defined (MIPS1)
! #define MachFlushCache		(*(mips_locore_jumpvec.flushCache))
! #define MachFlushDCache		(*(mips_locore_jumpvec.flushDCache))
! #define MachFlushICache		(*(mips_locore_jumpvec.flushICache))
  #define MachSetPID		(*(mips_locore_jumpvec.setTLBpid))
  #define MIPS_TBIAP()		(*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
  #define MIPS_TBIS		(*(mips_locore_jumpvec.TBIS))
  #define MachTLBUpdate		(*(mips_locore_jumpvec.tlbUpdate))
- #define MachHitFlushDCache	mips3_HitFlushDCache
  #define wbflush()		(*(mips_locore_jumpvec.wbflush))()
  #define proc_trampoline		(mips_locoresw[1])
  #endif
--- 162,173 ----
  #define wbflush()		mips1_wbflush()
  #define proc_trampoline		mips1_proc_trampoline
  #endif
  
! #if defined(MIPS3) && defined(MIPS1)
  #define MachSetPID		(*(mips_locore_jumpvec.setTLBpid))
  #define MIPS_TBIAP()		(*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
  #define MIPS_TBIS		(*(mips_locore_jumpvec.TBIS))
  #define MachTLBUpdate		(*(mips_locore_jumpvec.tlbUpdate))
  #define wbflush()		(*(mips_locore_jumpvec.wbflush))()
  #define proc_trampoline		(mips_locoresw[1])
  #endif
Index: mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.68
diff -c -r1.68 locore_mips3.S
*** mips/locore_mips3.S	2001/05/30 15:24:34	1.68
--- mips/locore_mips3.S	2001/06/11 19:11:18
***************
*** 1667,1673 ****
   * mips3_HitFlushDCache --
   *
   *	void mips3_HitFlushDCache(addr, len)
!  *		vaddr_t addr, len;
   *
   *	Flush data cache for range of addr to addr + len - 1.
   *	The address can be any valid virtual address as long
--- 1667,1674 ----
   * mips3_HitFlushDCache --
   *
   *	void mips3_HitFlushDCache(addr, len)
!  *		vaddr_t addr;
!  *		vsize_t len;
   *
   *	Flush data cache for range of addr to addr + len - 1.
   *	The address can be any valid virtual address as long
***************
*** 1928,1934 ****
   * mips3_HitFlushDCache_2way --
   *
   *	void mips3_HitFlushDCache_2way(addr, len)
!  *		vaddr_t addr, len;
   *
   *	Flush data cache for range of addr to addr + len - 1.
   *	The address can be any valid virtual address as long
--- 1929,1936 ----
   * mips3_HitFlushDCache_2way --
   *
   *	void mips3_HitFlushDCache_2way(addr, len)
!  *		vaddr_t addr;
!  *		vsize_t len;
   *
   *	Flush data cache for range of addr to addr + len - 1.
   *	The address can be any valid virtual address as long
Index: mips/mips_machdep.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.117
diff -c -r1.117 mips_machdep.c
*** mips/mips_machdep.c	2001/05/31 02:06:26	1.117
--- mips/mips_machdep.c	2001/06/11 19:11:19
***************
*** 137,142 ****
--- 137,143 ----
  	mips1_FlushCache,
  	mips1_FlushDCache,
  	mips1_FlushICache,
+ 	NULL,
  	mips1_SetPID,
  	mips1_TBIAP,
  	mips1_TBIS,
***************
*** 183,188 ****
--- 184,190 ----
  	mips3_FlushCache,
  	mips3_FlushDCache,
  	mips3_FlushICache,
+ 	mips3_HitFlushDCache,
  	mips3_SetPID,
  	mips3_TBIAP,
  	mips3_TBIS,
***************
*** 487,492 ****
--- 489,500 ----
  			mips3_locore_vec.flushCache = mips3_FlushCache_2way;
  			mips3_locore_vec.flushDCache = mips3_FlushDCache_2way;
  			mips3_locore_vec.flushICache = mips3_FlushICache_2way;
+ 			/*
+ 			 * XXX 2-way version does not yet handle L2 cache.
+ 			 */
+ 			if (mips_L2CachePresent == 0)
+ 				mips3_locore_vec.hitflushDCache =
+ 				    mips3_HitFlushDCache_2way;
  		}
  		mips3_vector_init(mips3_csizebase);
  		memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));