Subject: Re: NOTICE: thorpej-mips-cache branch will be merged today
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 11/20/2001 18:56:02 
<cgd@broadcom.com> pointed out;

> I notice in your diff you say:
>
> +# Invalid combinations are     
> +#  * MIPS1_3000 && (MIPS1_3900 || MIPS1_3920)
> +#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_4100
> +#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_5900
> +#  * MIPS3_4100 && MIPS3_5900
>
> Why are these actually invalid combinations?  (that seems bogus...)

How about categorize and collerate the functional aspect of CPU designs
instead of patch works to fill holes like that?

- TLB
    R3KTLB or R4KTLB (possibly R4KTLB64 for LP64)
- cache 
    R3KCACHE, R4KCACHE (, R5KCACHE) or TX39CACHE ...
- FP registers
    FPPAIRED32 (thirty-two 32bit), FPDOUBLE (thirty-two 64bit) or FPSINGLE (sorta)
- others necessary...

Toru Nishimura