On Sun, Dec 16, 2001 at 11:40:36PM +0900, TAKEMURA Shin wrote:

 > I've made the patch (attached). I'd like to commit the patch
 > if no one objects.

It's fine, but please don't include the MIPS3_4100 #ifdef.  (Such
#ifdef's will be introduced, but not until Simon and I work out
the strategy for it).

 > 
 > Takemura
 > 
 > sys/arch/mips/mips/cache.c:
 > 
 > mips_config_cache(void)
 > {
 >         /*
 >          * Configure primary caches.
 >          */
 >         switch (MIPS_PRID_IMPL(cpu_id)) {
 > <snipped>
 >         case MIPS_R4000:
 >         case MIPS_R4100:
 >         case MIPS_R4300:
 > + #ifdef MIPS3_4100
 > +               /*
 > +                * Vr4131 has cpu_id=0x0c80
 > +                * and R4600 style 2-way set-associative cache
 > +                */
 > +               if (!(MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
 > +                   (MIPS_PRID_REV(cpu_id) & 0x80))) {
 > + #endif
 >                 mips_picache_ways = 1;
 >                 mips_pdcache_ways = 1;
 > <snipped>
 >                 /* Virtually-indexed cache; no use for colors. */
 >                 break;
 > + #ifdef MIPS3_4100
 > +               }
 > +               /* fall through if CPU is Vr4131 */
 > + #endif
 > 
 >         case MIPS_R4600:
 >         case MIPS_RM5200:
 >                 mips_picache_ways = 2;
 >                 mips_pdcache_ways = 2;
 > 
 > EOF
 > 
 > 

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>