Simon Burge <simonb@wasabisystems.com> writes:
> Takao Shinohara wrote:
> 
> > > +void
> > > +mipsNN_icache_sync_range_index_16_4way(vaddr_t va, vsize_t size)
> > > [ ... ]
> > 
> > cache ops for other ways(2,3,4) are missing.
> > 
> > > +void
> > > +mipsNN_icache_sync_range_index_32_4way(vaddr_t va, vsize_t size)
> > > [ ... ]
> > 
> > ditto.
> 
> To date, all the mips32 and mips64 CPUs I've seen are 4-way associative.
> The cache size detection code will panic if a CPU isn't 4-way.

You missed the point.

I did not meant to say,

	"Hey, you forgot 2way(3way) cache configs!"

My intention was, you need additional lines, such as;

		cache_op_r4k_line(w2va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
		cache_op_r4k_line(w3va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
		cache_op_r4k_line(w4va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
		w2va += 16;
		w3va += 16;
		w4va += 16;

--- Takao Shinohara