I've prepared patch for R5900. Is this OK?
---
UCHIYAMA Yasushi
uch@vnop.net

Index: include/locore.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/locore.h,v
retrieving revision 1.59
diff -u -r1.59 locore.h
--- include/locore.h	2002/03/05 15:36:51	1.59
+++ include/locore.h	2002/03/07 15:40:36
@@ -219,7 +219,7 @@
 #define MachTLBUpdate		mips1_TLBUpdate
 #define wbflush()		mips1_wbflush()
 #define proc_trampoline		mips1_proc_trampoline
-#elif !defined(MIPS1) &&  defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64)
+#elif !defined(MIPS1) &&  defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900)
 #define MachSetPID		mips3_SetPID
 #define MIPS_TBIAP()		mips3_TBIAP(mips_num_tlb_entries)
 #define MIPS_TBIS		mips3_TBIS
@@ -241,6 +241,13 @@
 #define MachTLBUpdate		mips64_TLBUpdate
 #define proc_trampoline		mips64_proc_trampoline
 #define wbflush()		mips64_wbflush()
+#elif !defined(MIPS1) &&  defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900)
+#define MachSetPID		mips5900_SetPID
+#define MIPS_TBIAP()		mips5900_TBIAP(mips_num_tlb_entries)
+#define MIPS_TBIS		mips5900_TBIS
+#define MachTLBUpdate		mips5900_TLBUpdate
+#define proc_trampoline		mips5900_proc_trampoline
+#define wbflush()		mips5900_wbflush()
 #else
 #define MachSetPID		(*(mips_locore_jumpvec.setTLBpid))
 #define MIPS_TBIAP()		(*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
Index: mips/db_interface.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/db_interface.c,v
retrieving revision 1.41
diff -u -r1.41 db_interface.c
--- mips/db_interface.c	2002/03/05 15:43:25	1.41
+++ mips/db_interface.c	2002/03/07 15:40:38
@@ -350,7 +350,11 @@
 
 		for (i = 0; i < mips_num_tlb_entries; i++) {
 #if defined(MIPS3)
+#if defined(MIPS3_5900)
+			mips5900_TLBRead(i, &tlb);
+#else
 			mips3_TLBRead(i, &tlb);
+#endif
 #elif defined(MIPS32)
 			mips32_TLBRead(i, &tlb);
 #elif defined(MIPS64)
Index: mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.76
diff -u -r1.76 locore_mips3.S
--- mips/locore_mips3.S	2002/03/05 15:50:59	1.76
+++ mips/locore_mips3.S	2002/03/07 15:40:41
@@ -150,6 +150,7 @@
  *----------------------------------------------------------------------------
  */
 LEAF(mips3_wbflush)
+XLEAF(mips5900_wbflush)
 XLEAF(mips32_wbflush)
 XLEAF(mips64_wbflush)
 	nop
Index: mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.1
diff -u -r1.1 mipsX_subr.S
--- mips/mipsX_subr.S	2002/03/05 15:51:00	1.1
+++ mips/mipsX_subr.S	2002/03/07 15:40:50
@@ -242,6 +242,11 @@
 #define	MIPSX(name)	mips3_/**/name
 #endif
 
+#if defined(MIPS3_5900)
+#undef MIPSX
+#define	MIPSX(name)	mips5900_/**/name
+#endif
+	
 #if defined(MIPS32)
 #define	MIPSX(name)	mips32_/**/name
 #endif
Index: mips/mips_machdep.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.122
diff -u -r1.122 mips_machdep.c
--- mips/mips_machdep.c	2002/03/05 15:53:00	1.122
+++ mips/mips_machdep.c	2002/03/07 15:40:57
@@ -170,11 +170,12 @@
 #if defined(MIPS3)
 #if defined(MIPS3_5900)
 static void	r5900_vector_init(void);
+extern long	*mips5900_locoresw[];
 #else
 static void	mips3_vector_init(void);
-#endif
 extern long	*mips3_locoresw[];
 #endif
+#endif
 
 #if defined(MIPS32)
 static void	mips32_vector_init(void);
@@ -436,6 +437,7 @@
 #endif /* MIPS1 */
 
 #if defined(MIPS3)
+#ifndef MIPS3_5900	/* XXX */
 /*
  * MIPS III locore function vector
  */
@@ -448,7 +450,6 @@
 	mips3_wbflush,
 };
 
-#ifndef MIPS3_5900	/* XXX */
 static void
 mips3_vector_init(void)
 {
@@ -827,15 +828,19 @@
 #if defined(MIPS3)
 	case CPU_ARCH_MIPS3:
 	case CPU_ARCH_MIPS4:
+#ifdef MIPS3_5900	/* XXX */
 		mips3_cp0_wired_write(0);
-		mips3_TBIA(mips_num_tlb_entries);
+		mips5900_TBIA(mips_num_tlb_entries);
 		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
-#ifdef MIPS3_5900	/* XXX */
 		r5900_vector_init();
-#else
+		memcpy(mips_locoresw, mips5900_locoresw, sizeof(mips_locoresw));
+#else /* MIPS3_5900 */
+		mips3_cp0_wired_write(0);
+		mips3_TBIA(mips_num_tlb_entries);
+		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
 		mips3_vector_init();
-#endif /* MIPS3_5900 */
 		memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));
+#endif /* MIPS3_5900 */
 		break;
 #endif
 #ifdef MIPS32
Index: mips/trap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/trap.c,v
retrieving revision 1.168
diff -u -r1.168 trap.c
--- mips/trap.c	2002/03/05 15:55:41	1.168
+++ mips/trap.c	2002/03/07 15:41:00
@@ -1036,13 +1036,13 @@
 #endif	/* MIPS1 */
 
 /* XXX simonb: need mips32 and mips64 checks here too */
-#ifdef MIPS3		/* r4000 family (mips-III cpu) */
+#if defined(MIPS3) && !defined(MIPS3_5900) /* r4000 family (mips-III cpu) */
 	Name(mips3_KernGenException),
 	Name(mips3_UserGenException),
 	Name(mips3_SystemCall),
 	Name(mips3_KernIntr),
 	Name(mips3_UserIntr),
-#endif	/* MIPS3 */
+#endif	/* MIPS3 && !MIPS3_5900 */
 
 	Name(mips_idle),
 	Name(cpu_switch),