Subject: Re: New MIPS cache code vs. R5k secondary caches...
To: Rafal Boni <rafal@attbi.com>
From: Jason R Thorpe <thorpej@wasabisystems.com>
List: port-mips
Date: 09/20/2002 16:54:40
On Fri, Sep 20, 2002 at 07:43:14PM -0400, Rafal Boni wrote:
> Actually, looking at the bus transaction in the "Sec. Cache Interface", it
> does look that way -- all that's emitted on the bus is the tag, the index
> and a write command on the SysCmd bus.
Ok, that makes a lot more sense. So, it's all pretty easy, then.
> If you have a copy of "See MIPS Run" and can see if it sheds any light on
> this quickly, feel free to drop me a line, or I'll see if I can dig it up
> when my stuff arrives from storage next week 8-)
It doesn't shed much light on anything in this area, at least at a quick
glance...
--
-- Jason R. Thorpe <thorpej@wasabisystems.com>