Stephen Ma <stephenm@employees.org> said;

> Toru> So, setting SR with the value there makes two bad things; to set
> Toru> EXL condition and start FPU mistakenly.  These bits must be
> Toru> turned off before MTC instruction updates SR.
>
> The patch only uses the IM mask bits from the SR value saved in the
> exception frame. The rest of the COP0 SR bits are preserved.

Sorry, it's my misunderstanding.

Chuck Silvers <chuq@chuq.com> said;

> one thing to be careful of here:  you must not allow nested interrupts
> of the same level as the one you're currently processing as long as the
> interrupt handler is using any stack space.  

I would like to make a similar change there.  Preserved IE, but IM cleared.
In R3000 case, copy IEp to IEc.  R4000 case, leave IE as it was.  Munch
outstanding interrupt conditions and re-enabling distinct IM bits (if
necessary) will be cpu_intr()'s responsibility.

Toru Nishimura/ALKYL Technology