On Sun, Sep 28, 2003 at 11:34:41PM +0900, Izumi Tsutsui wrote:

> >>  device-major	ksyms		char 77			ksyms
> >> +device-major	lpt		char 78			lpt
> >>  device-major	pf		char 78			pf
> >>  device-major	crypto		char 79			opencrypto

*blink*

At the time I added lpt support, 78 was free.  Yes, merge botch.

> These functions are refered from other sources, so they should be declared
> in crimevar.h.

Agreed.

> >> +	crime_sc->iot = 1;
> 
> Maybe we should have some macro for MD bus space tag values.
> (they are used only in bus.c:bus_space_{read,write}_{1,2}() ?)

sgimips bus_space foo is mostly fake.  Until a little while ago, the bus_space
routines were front_ends for *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(x)
(and, actually, still are mostly).  This needs to change for proper r10k
support, but for now I think there is no serious problem with the code
as it stands.

> crime_intr_mask() always uses the global crime_sc, so we don't have to pass
> it from callers.

Agreed.

(also, agreed for the rest of the function declaration nits -- it's been a long
day and, thanks to IP-R/Softbank foo, tomorrow promises to be even worse)

> >> +++ ip32/sys/arch/sgimips/sgimips/machdep.c
> 
> This file contains flush_pcache_anyway hack and r5ksc/r10k stuff.
> Which changes should be done for intermediate commit?

Assuming no r5ksc/r10k, we'd have to disable the sc and punt for r10k.  The
routine should look like this:

void mips_machdep_cache_config(void)
{
        volatile u_int32_t cpu_config;

        arcbios_tree_walk(mips_machdep_find_l2cache, NULL);

        switch (MIPS_PRID_IMPL(cpu_id))
        {
        case MIPS_R4600:
                /* r4600 is on Indy-class machines only.  Disable and
                   flush pcache. */ 
#if defined(IP22)
                mips_sdcache_size = 0;
                mips_sdcache_line_size = 0;
                ip22_sdcache_disable();
#endif  
                break;
        case MIPS_R5000:
                mips_sdcache_size = 0;
                mips_sdcache_line_size = 0;
                cpu_config = mips3_cp0_config_read();
                cpu_config &= ~MIPS3_CONFIG_SE;
                mips3_cp0_config_write(cpu_config);
                break;
        case MIPS_R10000:
                panic("r10k support has not yet been committed");
                break;
        default:
                printf("Don't know how to configure SC on this platform.\n");
                break;
        }
}

(not compile-tested, just a quick re-edit of the code for demonstration
purposes)

> On _LP64, long and unsigned long are 64bit, so I don't think
> this change is needed.

This snuck in while I was trying to build an elf64 kernel, and can be
disposed of.

> >> +++ ip32/sys/arch/mips/mips/genassym.cf
>  : 
> >> -#if !defined(__mips_n32) && !defined(__mips_n64)
> >> +if !defined(__mips_n32) && !defined(__mips_n64)
> >>  # Use these only in code used by 32-bit processors (which cannot
> >>  # use new-ABI).
>  :
> >> -#endif
> >> +endif
> 
> Is these '#'s are just typo, or intentional?
> Does this cause any problem for now?

They seem to have been typos.  They caused problems while compiling for elf64.

> Still I'll leave them because we should have discussion
> with portmasters and build maintainers what kernel sets
> we should have etc.

Fair enough.  Soren, would you be able to provide input?

(personally, I feel that the install kernels should be moved to
installation/whatever and that the ecoff kernels should be built for IP22
only)

Thanks for providing feedback.  I'm always interested in improving my code ;)

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)