Takao Shinohara wrote:

> current implementation of R10000 cache op (arch/mips/cache_r10k.c rev. 1.1)
> is broken. So, I wrote new implementation independent to Kiyohara-san.

What exactly is broken with the current R10k implementation?

From your diff, all R1{0,2,4}k have 64-byte i-cache lines and
32-byte d-cache lines?  You also remove the use of the multi-line
cache_r10k_op_Nlines_* ops too - was there no performance advantage
in the unrolling?

The new cache_r10k.c looks right at a glance, but I'm curious as
to what was currently broken.

Cheers,
Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD Support and Service:         http://www.wasabisystems.com/