Subject: Re: Removing MIPS3_L2CACHE_ABSE
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 12/13/2003 12:51:03
Just for your information. To make technologically correct the following if-clause;
if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
should be instead;
if (L1cache-is-VIPT && total-ammount-of Dcache/way-count > 4KB)
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
As I repeatedly pointed out, the zero_page/copy_page implementation is an absolute
mistake for VIPT cache.
Toru Nishimura/ALKYL Technology