Subject: Re: Removing MIPS3_L2CACHE_ABSE
To: Toru Nishimura <locore32@gaea.ocn.ne.jp>
From: Christopher SEKIYA <wileyc@rezrov.net>
List: port-mips
Date: 12/13/2003 13:20:01
On Sat, Dec 13, 2003 at 12:51:03PM +0900, Toru Nishimura wrote:
> if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
> mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
>
> should be instead;
>
> if (L1cache-is-VIPT && total-ammount-of Dcache/way-count > 4KB)
> mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
Maybe I'm just being thick, but aren't all post-r3k L1 caches VIPT?
That being the case, would the logic look like this:
if ( !(MIPS_PRID_IMPL(cpu_id) == MIPS_R3000) && mips_sdcache_line_size > 4096)
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
?
-- Chris
GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5 938E 023E EEFB FEB9 DE7F)