"Toru Nishimura" wrote:

> Simon Burge said;
> 
> > Note that from NetBSD's point of view, the Au1000 cache is fully
> > coherent, even when fetching in to the instruction cache.  Thus
> > there is no need for any specific cache handling at all.
> 
> It's interesting. What's the difference between the IDT and Au?

I'm not sure - I've not really looked at the IDT cache.  The issue
of cache coherency is different to cache organisation though.  I know
of no other CPUs in the MIPS world where both the I and D caches are
totally coherent.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD Support and Service:         http://www.wasabisystems.com/