"Alex Pelts" wrote:

> Some of the processors will allow you to make it write-trough instead of 
> write-back. I am not sure if the cube is of that variety but I think it 
> is not. Although I dont know if that would help.
> The closest thing to disabling cache would be to allocate buffers for 
> suspected operation from Kseg1 segment which is uncached. Unfortunately 
> I dont think it is possible as this memory also unmapped which would 
> kill its use in user space. Although it might be possible to setup some 
> specific test with hacked kernel just to find this bug.
> 
> Is that a bad idea ?

Thinking about this a little, I guess we could just map all TLB pages
uncached if we want to mostly disable caches.  Could someone try
changing the this line in sys/arch/mips/include/mips3_pte.h (around
line 135):

  #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3)

to 

  #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(2)

For the RM5200, using 1 or 2 will also select write-through modes
so that may well be worth trying too.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD Support and Service:         http://www.wasabisystems.com/