>> (R4000/4400) SC/MC L2 cache tag.  It contains VA[14:12] to detect virtual
>> alias condition.

This is THE whole issue.  The VA 3bit have enoumous significance.

1. 16KB/direct mapped case
The least significant 2 bits distinguish which VA page belongs to
"indexing groups"  0,1,2 or 3.  VA range is broken into 4 page
iterations.

2, 16KB/2way set associative case
The least significant bit distinguishs two groups, 0 or 1.  VA range is
covered by 2 page iterations.

3. 16KB/4way set associative case
VA range is never broken into groups.  The 3 bits are all zeros.  This
is effective PIPT cache machinary.

Au1, RM7000 and descenders and R3000 belongs to the 3rd case.
(Note; SB-1 cache is pretty different.  It's fine they realized the
cache design importance, however, I think their decision would never
be main-street MIPS design.)

Toru Nishimura/ALKYL Technology